The invention relates generally to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a semiconductor device, wherein resistivity can be reduced by making uniform the root mean square (RMS) roughness resulting from the grain size of a metal layer at the interface between the metal layer and a conductive layer in forming a gate electrode layer having a stack structure.
In general, in semiconductor devices, a gate electrode has a stack structure of a conductive layer and a metal layer. The conductive layer is generally formed from polysilicon and the metal layer is generally formed from tungsten silicide (WSix). After the metal layer is formed, an annealing process is performed in order to reduce resistance of the metal layer and to improve the electrical properties of subsequently-formed word lines.
However, the annealing process is performed at high temperature, and the grain size of the metal layer therefore may become irregular. If the grain size of the metal layer becomes irregular, the RMS roughness of the interface of the metal layer and the conductive layer can be increased, so resistance may be increased and a gate patterning process may become difficult.